//-----------------------------------------------------------------------------
//  Copyright (c) 2013 by HangZhou HenqgQiao Design Corporation. All rights reserved.
//
//  Project  : 
//  Module   : 
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths


module AURG_FIFO_RAM64_8_8(
   input                      CLKA,
   input                      WEA,
   input[2:0]                 ADDRA,
   input[7:0]                 DINA,

   input                      CLKB,
   input[2:0]                 ADDRB,
   output reg[7:0]            DOUTB
   );

reg[7:0]            RAM_VECTOR_0, RAM_VECTOR_1, RAM_VECTOR_2, RAM_VECTOR_3;
reg[7:0]            RAM_VECTOR_4, RAM_VECTOR_5, RAM_VECTOR_6, RAM_VECTOR_7;
reg[7:0]            RAM_RD_VECTOR;


always @(posedge CLKA) begin
   if ( WEA==1'b1 ) begin
      case (ADDRA[2:0])
      3'b000: RAM_VECTOR_0[7:0]              <= DINA[7:0];
      3'b001: RAM_VECTOR_1[7:0]              <= DINA[7:0];
      3'b010: RAM_VECTOR_2[7:0]              <= DINA[7:0];
      3'b011: RAM_VECTOR_3[7:0]              <= DINA[7:0];
      3'b100: RAM_VECTOR_4[7:0]              <= DINA[7:0];
      3'b101: RAM_VECTOR_5[7:0]              <= DINA[7:0];
      3'b110: RAM_VECTOR_6[7:0]              <= DINA[7:0];
      3'b111: RAM_VECTOR_7[7:0]              <= DINA[7:0];
      default: ;
      endcase
   end
end


always @(posedge CLKB) begin
      case (ADDRB[2:0])
      3'b000: RAM_RD_VECTOR[7:0]             <= RAM_VECTOR_0[7:0];
      3'b001: RAM_RD_VECTOR[7:0]             <= RAM_VECTOR_1[7:0];
      3'b010: RAM_RD_VECTOR[7:0]             <= RAM_VECTOR_2[7:0];
      3'b011: RAM_RD_VECTOR[7:0]             <= RAM_VECTOR_3[7:0];
      3'b100: RAM_RD_VECTOR[7:0]             <= RAM_VECTOR_4[7:0];
      3'b101: RAM_RD_VECTOR[7:0]             <= RAM_VECTOR_5[7:0];
      3'b110: RAM_RD_VECTOR[7:0]             <= RAM_VECTOR_6[7:0];
      3'b111: RAM_RD_VECTOR[7:0]             <= RAM_VECTOR_7[7:0];
      default: ;
      endcase
end

always @(posedge CLKB) begin
      DOUTB[7:0]                             <= RAM_RD_VECTOR[7:0];
end

endmodule
